1. Field of the Invention
The present invention relates to a phase switching circuit, and more particularly, to a multiple-phase switching circuit capable of switching bi-directionally.
2. Description of the Related Art
In a data recovery system, received high-frequency signal, which is declined by noise, can be recovered by circuit components such as an equalizer. However, correct sampling of data stream still strongly depends on precise control of clock signal. Alignment of the rising and/or falling edges of the clock signal to the middle of each bit data of the data stream is desired, in order to ensure correct sampling. Conventionally, a continuous time phase locked loop (PLL) is employed in a data recovery system to achieve the aforementioned alignment. However, data recovery using the continuous time PLL suffers from longer lock time, phase noise, as well as single receiving channel.
Consequently, multiple-phase system is adapted to embodying the clock recovery system. The alignment of the rising/falling edges of the clock signal to the data stream can be achieved by selecting among multiple-phase signals a proper phase signal in the multiple-phase system. Faster lock-in time can be expected using multiple-phase system. The influence of noise can also be minimized due to mostly digitized operations. Moreover, the multiple-phase clock signals enable multiple receiving channel applications.
FIG. 1A shows a clock recovery system employing a multiple-phase switching circuit. The received data stream and the system clock are inputted and processed by a digital signal processor (DSP) 10 to obtain the timing information between the data stream and the clock in determining whether the clock leads ahead or lags behind the desired sampling point. An up/down signal is then sent to a multiple-phase switching circuit 11 to accordingly select a recovery clock from a plurality of clock signals with different phases as the system clock. Such selected system clock is utilized as the sampling clock of the received data stream.
FIG. 1B shows a timing diagram of the data stream and the plurality of clock signals (CK0–CK7) with different phases. As shown in FIG. 1B, the most suitable clock signal for data sampling is the clock signal CK4 whose rising edges are aligned to the desired middle point of each bit data of the data stream. As a result, if in the first place the system clock is selected to be CK2, as shown in FIG. 1C, the DSP 10 will control the multiple-phase switching circuit 11 to sequentially switch through CK3 to CK4, also shown in FIG. 1C, and eventually locks the system clock at CK4. However, the smooth switching procedure shown in FIG. 1C is the ideal case, while FIG. 1D illustrates a more realistic situation, wherein undesirable glitch and/or spike phenomenon 13 can be seen when switching between clock signals with different phases occurs. In order to avoid such glitch/spike phenomenon, conventionally single direction phase switching (either upwards or downwards) is employed, which, however, in turn increases the average lock-in time.
The multiple-phase switching circuit can also be employed in a frequency synthesizer as shown in FIG. 2B, in the stead of a conventional frequency synthesizer utilizing a pulse swallower 24, as shown in FIG. 2A, which is well known to those skilled in the art. Referring to FIG. 3, by employing the conventional frequency synthesizer in FIG. 2A, a signal with frequency f0=f1−1/Tp, which in this particular case can be a non-integer multiple of f1=1/Ts in FIG. 3(a), can be synthesized with pulse swallowing, as shown in FIG. 3(b). However, larger clock jitter tends to be induced through direct pulse swallowing. Such jitter phenomenon may be minimized by adopting the frequency synthesizer utilizing a multiple-phase switching circuit 21 as shown in FIG. 2B. A multiple-phase voltage controlled oscillator 25 generating a plurality of clock signals with different phases, as well as the multiple-phase switching circuit 21, whose operation is similar to the multiple-phase switching circuit 11 in the data recovery system, are utilized in the frequency synthesizer to synthesize the signal with frequency f0=f1−1/Tp, by “gradually” switching the outputted signal of the multiple-phase switching circuit 21 through clock signals with different phases, as shown in FIG. 3(c). As such, jitter caused by pulse swallowing can be significantly reduced.